As a conventional analog switch circuit, for example, an analog switch circuit, which is used in an input device as shown in FIG. 1A, is known. This input device comprises a power source 12, input signal sources 13, 14, current limiting resistance 15, 16, electrostatic protecting diodes 1, 2, 31, 33, analog switches 3, 28, and a comparator 17.
The analog switches 3, 28, as shown in FIG. 1B, comprise a P-channel transistor 21 and a N-channel transistor 24 whose drains and sources are connected to each other, and an inverter 27 which inverts a signal from a terminal 26 and then applies it to the gate of the P-channel transistor 21.
As shown in FIG. 2A, the analog switches 3, 28 are so fabricated that N.sup.- layers 20, 22 separated by a P.sup.+ separating layer 18 for preventing from latching up are formed on a P-substrate 19 and the gate electrodes of the P-channel transistor 21 in the N.sup.- layer 20 and the N-channel transistor 24 in the P-layer 23 formed in the N.sup.- layer 22 are connected to each other through the inverter 27.
Hereupon, the source, drain and back gate of the P-channel transistor 21 correspond to the emitter, collector and base, respectively, of a PNP transistor 4, where the back gate, i.e., the base is connected to a power source potential V.sub.DD. Also, the drain, source and back gate of the N-channel transistor 24 correspond to the emitter, collector and base, respectively, of a NPN transistor 5, where the back gate, i.e., the base is connected to a ground potential V.sub.SS. Thus, the analog switches 3, 28 have the PNP transistor 4 and NPN transistor 5 as parasitic transistors. Therefore, they can be, as shown in FIG. 2B, represented by the PNP transistor 4 and NPN transistor 5 whose emitters and collectors are connected to each other.
The operation of this analog switch circuit will be explained below. First, taking the case that the potentials of the input signal sources 13, 14 lie between the power source potential V.sub.DD and the ground potential V.sub.ss, when the analog switch 3 is OFF and the analog switch 28 is ON, the potential of the input signal source 14 is, as it is, applied to the input terminal of the comparator 17, and its level is compared to a reference potential `ref`, and then the comparison result is output.
Next, taking the case that the potential of the input signal source 13 is higher than the power source potential V.sub.DD and the potential of the input signal source lies between the power source potential V.sub.DD and the ground potential V.sub.SS, when the analog switch 3 is OFF and the analog switch 28 is ON, the current flows through the current limiting resistance 15, electrostatic protecting diode 1 into the power source 12. However, as seen from FIG. 2A, the emitter, base of the parasitic PNP transistor 4 are connected parallel to the electrostatic protecting diode 1. Therefore, the current flows into the base of the PNP transistor 4, and the PNP transistor 4 is turned on.
As a result, the current flows from the input signal source 13 through the current limiting resistance 15, PNP transistor 4, the output terminal 49 of the analog switch 3, analog switch 28 and current limiting resistance 16 into the input signal source 14. Thereby, the input potential of the comparator 17 becomes higher than the potential of the input signal source 14. This may cause a failure in the output of correct comparison data from the comparator 17.
To suppress such a phenomenon, Japanese patent application laid-open No.58-68319(1983) discloses an analog switch circuit. In this circuit, diodes 50, 51 are connected between a power source potential V.sub.DD and a ground potential V.sub.SS of the integrated circuit and a power source 12, and diodes 52, 52 with a low forward voltage drop such as a Schottky barrier diode are connected between input signal sources 13, 14 and a ground potential V.sub.SS. Thereby, even when the voltage of the power source 12 is not supplied and the voltages of the input signal sources 13, 14 are supplied, the analog switches 3, 28 can be kept to be turned off.
In this analog switch circuit, the current flowing from the input signal source 13 through the current limiting resistance 15, the emitter and base of the PNP transistor 4 into the power source 12 is blocked by the diode 50. Also, in the potential relation, when the input signal source 14 is higher than the power source(positive potential) and the input signal source 13 is lower than the power source 12(negative potential), the current path is formed from the input signal source 14 through the current limiting resistance 16, the emitter and base of a parasitic PNP transistor 39(or an electrostatic protecting diode 31), the power source V.sub.DD of IC, a control circuit(not shown) or a leakage in IC, the ground potential V.sub.SS of IC, the base and emitter of the parasitic NPN transistor 5 and the current limiting resistance 15 to the input signal source 13.
In this case, as shown in 3B, a parasitic diode 54 and a parasitic NPN transistor 55 can be turned on by the leakage current flowing into a parasitic NPN transistor 56 to flow the current therethrough. However, bypassing the current by the diodes 52, 53 with a low forward voltage drop, the parasitic diode 54 and the parasitic NPN transistor 55 can be kept to be off to prevent the current from flowing.
On the other hand, Japanese patent application laid-open No.63-144620(1988) discloses another type of an analog switch circuit as shown in FIG. 4. As shown in FIG. 4, a P-channel transistor 60 is connected between analog switches 3, 57 and between them and a power source potential V.sub.DD a N-channel transistor 61 is connected between analog switches 58, 59 and a ground potential V.sub.SS, and the terminals of the analog switch 3, 58 are connected through the current limiting resistance 15 to the input signal source 13.
In this circuit, when the analog switches 3, 57, 58 and 59 are individually OFF, the P-channel transistor 60 and the N-channel transistor 61 are turned on. Thus, when the potential of the input signal source 13 is higher than the potential V.sub.DD of the power source 12, a parasitic PNP transistor 62 in the analog switch 58 can operate, but, keeping the input potential of the following analog switch 59 less than the power source potential V.sub.DD by turning on the N-channel transistor 61 can prevent a parasitic PNP transistor 63 in the analog switch 59 from operating.
Also, in this circuit, by flowing the current by the operation of the parasitic PNP transistor 62 through the N-channel transistor 61 which is turned on into the ground potential V.sub.SS, the voltage of an input terminal 35 is lowered as much as possible, and, by decreasing the base current of the parasitic PNP transistor 4 in the analog switch 3 as much as possible, the collector current of the PNP transistor 4 is decreased, and, further, by turning on the P-channel transistor 60, the emitter-base of the parasitic PNP transistor 64 in the following analog switch 57 is short-circuited. Thereby, the operation of the parasitic PNP transistor 64 can be prevented.
Furthermore, Japanese patent application laid-open No.1-236731(1989) discloses another type of an analog switch circuit as shown in FIG. 5. As shown in FIG. 5, a N-channel transistor(or P-channel transistor) 65 is connected between cascade-connected analog switches 3, 57 and between them and a ground potential V.sub.DD (or a power source potential V.sub.DD), the input terminal of the analog switch 3 is connected through a current limiting resistance 15 to an input signal source 13, a N-channel transistor(or P-channel transistor) 68 is connected between cascade-connected analog switches 28, 67 and between them and the ground potential V.sub.SS (or the power source potential V.sub.DD), and the input terminal of the analog switch 28 is connected through a current limiting resistance 16 to an input signal source 14. Though Japanese patent application laid-open No.1-236731(1989) describes the case that the analog switch is turned on due to the relation between the back gate potential and the gate potential, the case that the analog switch is turned on due to the operation of the parasitic transistor is taken herein.
In this analog switch circuit, when the analog switches 3, 57(28, 67) are OFF, the N-channel transistor 65(68) is turned on. Thus, when the potential of the input signal source 13 is higher than the potential V.sub.DD of a power source 12, a parasitic PNP transistor 4 in the analog switch 3 can operate, but, keeping the input potential of the following analog switch 57 less than the power source potential V.sub.DD by turning on the N-channel transistor 65 can prevent a parasitic PNP transistor 64 in the analog switch 57 from operating.
When the potential of the input signal source 13 is lower than the ground potential V.sub.SS, a NPN transistor 5 in the analog switch 3 can operate, but, short-circuiting the base-emitter of a parasitic NPN transistor 66 in the following analog switch 57 by turning on the N-channel transistor 65 can prevent the parasitic NPN transistor 66 from operating.
However, in the conventional analog switch circuits, there is a problem that they need a number of elements. Though the analog switch circuit in FIG. 1A needs 6.times.n elements(the P-channel transistor, N-channel transistor and inverter composing the analog switch in the signal path, and the two electrostatic protecting diodes) to n inputs, the number of the elements is not so many.
On the contrary, the analog switch circuit in FIG. 3A needs (7.times.n+2) elements to n inputs. Also, the analog switch circuit in FIG. 4 needs 14.times.n elements to n inputs since one inverter is , which is not shown in FIG. 4, provided in the switching control signal path of four analog switches to one input. The analog switch circuit in FIG. 5 needs 9.times.n elements to n inputs since one inverter is, which is not shown in FIG. 5, provided in the switching control signal path of two analog switches to one input.
Also, in the conventional analog switch circuits, there is a problem that they need the current limiting resistances 15, 16 which may heat due to the operation of the parasitic transistor. The reason is that, though the current limiting resistances 15, 16 are necessary since excess current may flow due to the insertion of the diodes 1, 2 between the input terminal and the power source potential V.sub.DD and ground potential V.sub.SS, in case of the structure in FIG. 2A, the parasitic PNP transistor 67 generated among the P.sup.+ region, N.sup.- layer 20 and P substrate 19 may operate due to the current flowing from the P.sup.+ region to the power source potential V.sub.DD when the potential of the input signal source 13 is higher than that of the power source 12, or, in case of the structure in FIG. 3B, the parasitic NPN transistor 56 generated among the N.sup.- layer 20, P.sup.- layer 23 and N.sup.+ region may operate due to the current flowing from the ground potential V.sub.SS to the N.sup.+ region when the potential of the input signal source 13 is lower than the ground potential V.sub.SS. Therefore, depending on the current limiting resistance and the current amplification factor of the parasitic PNP transistor 67 or the parasitic NPN transistor 56, they may heat or be broken in the worst case. Even when the parasitic current does not cause the heating, it may cause a variation in the potential of the back gate of MOSFET, therefore undesirably affecting the high-precision IC.